Publication:
An FPGA implementation of 2-D CNN Gabor-type filter

Date
2007
Authors
Saatçı, Ertuğrul
Cesur, Evren
Tavşanoğlu, Vedat
Kale, İzzet
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IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
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Abstract

A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 x 60 can be processed without using any external RAM only with the block RAM.

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