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dc.contributor.authorSaatçı, Ertuğrul
dc.contributor.authorCesur, Evren
dc.contributor.authorTavşanoğlu, Vedat
dc.contributor.authorKale, İzzet
dc.date.accessioned2016-04-22T12:53:00Z
dc.date.available2016-04-22T12:53:00Z
dc.date.issued2007
dc.identifier.urihttp://hdl.handle.net/11413/1111
dc.description.abstractA field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 x 60 can be processed without using any external RAM only with the block RAM.tr_TR
dc.language.isoen_UStr_TR
dc.publisherIEEE, 345 E 47TH ST, NEW YORK, NY 10017 USAtr_TR
dc.relation2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3tr_TR
dc.titleAn FPGA implementation of 2-D CNN Gabor-type filtertr_TR
dc.typeArticletr_TR
dc.contributor.authorIDTR10488tr_TR
dc.contributor.authorIDTR36339tr_TR
dc.identifier.wos258708400071
dc.identifier.wos258708400071en


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